| Seznam |
| Téma: | VHDL design of the impulse generator |
|---|---|
| Vedoucí: | Radek Sedláček |
| Vypsáno jako: | Práce v týmu a její organizace |
| Popis: | Familiarise with the general principle of generating pulses on the FPGA circuits.
Main goal of this project is development a a pulse generator with nanosecond resolution. Solution to use FPGA. The parameters of the output signal is as follows: repetition frequency is adjustable in the range 10 MHz to 100 MHz, the pulse width can be set in the range of 1 to 20 ns with a step of 0.1 ns. Use VHDL language For synthesis. The topic is suitable for the students which have a basic knowledge of VHDL language. The project can be divided into following stages: 1/ theoretical study of the problem - select proper method for implementation 2/ hardware platform specification according the requirements 3/ implementation of one method of pulses generation in VHDL 4/ verification and testings on real hardware - measurement a final parameters 5/ documentation & report There are available a various evaluation boards for FPGA INTEL (Altera) and QUARTUS IDE. |
| Literatura: | 1/ https://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html 2/ http://www.j.sinap.ac.cn/nst/CN/article/downloadArticleFile.do?attachType=PDF&id=457 |
| Realizace: | VHDL code (IP core) for FPGA |
| Vypsáno dne: | 20.02.2017 |
| Max. počet studentů: | 4 |
| Přihlášení studenti: | |