| Seznam |
| Téma: | Implementation of synchronous detection algorithm in VHDL |
|---|---|
| Vedoucí: | Radek Sedláček |
| Vypsáno jako: | Práce v týmu a její organizace |
| Popis: | The main goal of the project is VHDL implementation of synchronous detection (SD) algorithm, which is important part of all lock-in amplifiers or vector voltmeters. Very important part of each synchronous detectors is output low pass filter to elimination of double frequency component in the frequency spectrum.
The project solution can be divided in a few parts: 1) design and implementation of PLL 2) design and implementation of output filters (IIR or FIR) 3) design and implementation of whole synchronous detector 4) testing (via test bench) and tuning of SD parameters (frequency working range, phase jitter, etc.) 5) documentation & report about project solution There is a possibility of the project extension - all important parameters of synchronous detector can be set by means of some communication interface (UART, LAN). The topic is suitable for the students which have a basic knowledge of VHDL language. There are available a various evaluation boards for INTEL ((Altera) FPGA and QUARTUS IDE. |
| Literatura: | 1/ http://measure.feld.cvut.cz/system/files/files/cs/vyuka/predmety/A3M38MSZ/SynchrDetectBW.pdf 2/ http://www.ijfcc.org/papers/225-E353.pdf |
| Realizace: | VHDL code + report (documentation) |
| Vypsáno dne: | 20.02.2017 |
| Max. počet studentů: | 4 |
| Přihlášení studenti: | |