Detail of the student project

List
Topic:50 Hz harmonic FPGA based generator with phase-locked loop
Supervisor:Radek Sedláček
Announce as:PTO
Description:Familiarize with the general principle of direct digital synthesis and principle ADPLL algorithm. Design of hardware and firmware generator, which will be able to phase lock to the input signal of the frequency, typically 50 Hz. As main control part, a FPGA circuit must be used. The firmware of FPGA will be written in VHDL. The initial development and testing may be based on usage of the development kit for the FPGA. There are expected at least the following outputs: electronic schema of generator, PCB design and assembly drawing. Create also a simple control application (on the Qt platform) for PC to set basic parameters such as amplitude or the frequency of the output signal. Finally make a short testing generator to verifying its parameters.
Date:20.02.2017
Max.number of students:4
 

Warning: the registration to the PTO can be canceled only by supervisor.
Responsible person: Petr Pošík