| Téma: | 50 Hz harmonic FPGA based generator with phase-locked loop
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| Vedoucí: | Radek Sedláček
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| Vypsáno jako: | Práce v týmu a její organizace
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| Popis: | Familiarize with the general principle of direct digital synthesis and principle ADPLL algorithm. Design of hardware and firmware generator, which will be able to phase lock to the input signal of the frequency, typically 50 Hz. As main control part, a FPGA circuit must be used. The firmware of FPGA will be written in VHDL. The initial development and testing may be based on usage of the development kit for the FPGA. There are expected at least the following outputs: electronic schema of generator, PCB design and assembly drawing. Create also a simple control application (on the Qt platform) for PC to set basic parameters such as amplitude or the frequency of the output signal. Finally make a short testing generator to verifying its parameters.
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| Literatura: | http://www.analog.com/media/en/analog-dialogue/volume-38/number-3/articles/all-about-direct-digital-synthesis.pdf
http://www.ijecse.org/wp-content/uploads/2012/12/Volume-2Number-1PP-94-101.pdf
https://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html
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| Realizace: | el. schema, PCB, VHDL firmware, Qt software
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| Vypsáno dne: | 20.02.2017
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| Max. počet studentů: | 4
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| Přihlášení studenti: |
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